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3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV)., , , , , , , , , and 3 other author(s). 3DIC, page 1-5. IEEE, (2009)Design issues and considerations for low-cost 3D TSV IC technology., , , , , , , , , and 24 other author(s). ISSCC, page 148-149. IEEE, (2010)Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC., , , , , and . DSD, page 729-734. IEEE Computer Society, (2008)Low-Power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator., , , , , , , , and . CICC, page 1-6. IEEE, (2012)Design Issues and Considerations for Low-Cost 3-D TSV IC Technology., , , , , , , , , and 27 other author(s). J. Solid-State Circuits, 46 (1): 293-307 (2011)22.5 A 4×20Gb/s WDM ring-based hybrid CMOS silicon photonics transceiver., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)Layout to Logic Defect Analysis for Hierarchical Test Generation., , , , and . DDECS, page 35-40. IEEE Computer Society, (2007)Wavelength locking of a Si ring modulator using an integrated drop-port OMA monitoring circuit., , , , , , and . A-SSCC, page 1-4. IEEE, (2015)