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Disambiguation of "Pasricha, Sudeep"

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Preemptive Resource Management for Dynamically Arriving Tasks in an Oversubscribed Heterogeneous Computing System.

, , , , , , , , , and . IPDPS Workshops, page 54-64. IEEE Computer Society, (2017)

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Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends., , , , and . VLSI Design, page 8. IEEE Computer Society, (2007)Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 28 (4): 554-567 (2009)VARSHA: variation and reliability-aware application scheduling with adaptive parallelism in the dark-silicon era., and . DATE, page 1060-1065. ACM, (2015)A co-synthesis methodology for power delivery and data interconnection networks in 3D ICs., and . ISQED, page 73-79. IEEE, (2013)Thermal-aware semi-dynamic power management for multicore systems with energy harvesting., and . ISQED, page 619-626. IEEE, (2013)A novel 3D graphics DRAM architecture for high-performance and low-energy memory accesses., and . ICCD, page 467-470. IEEE Computer Society, (2015)AURA: An application and user interaction aware middleware framework for energy optimization in mobile devices., , and . ICCD, page 168-174. IEEE Computer Society, (2011)Stochastically robust static resource allocation for energy minimization with a makespan constraint in a heterogeneous computing environment., , , , , , , , , and 1 other author(s). AICCSA, page 22-31. IEEE Computer Society, (2011)Utility Driven Dynamic Resource Management in an Oversubscribed Energy-Constrained Heterogeneous System., , , , , , , , , and . IPDPS Workshops, page 58-67. IEEE Computer Society, (2014)FABSYN: floorplan-aware bus architecture synthesis., , , and . IEEE Trans. VLSI Syst., 14 (3): 241-253 (2006)