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General Purpose Task-Dependence Management Hardware for Task-Based Dataflow Programming Models.

, , , , , , and . IPDPS, page 244-253. IEEE Computer Society, (2017)

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Automatic generation of loop scheduling for VLIW., , , and . PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications., , , , and . SAMOS, volume 5114 of Lecture Notes in Computer Science, page 53-64. Springer, (2008)Errata on "Measuring Experimental Error in Microprocessor Simulation"., , , , , , and . SIGARCH Computer Architecture News, 30 (1): 2-4 (2002)Exploiting instruction- and data-level parallelism., and . IEEE Micro, 17 (5): 20-27 (1997)Multicore: The View from Europe., and . IEEE Micro, 30 (5): 2-4 (2010)Virtual registers., , , and . HiPC, page 364-369. IEEE Computer Society, (1997)Implicit Transactional Memory in Kilo-Instruction Multiprocessors., , , , , , , and . Asia-Pacific Computer Systems Architecture Conference, volume 4697 of Lecture Notes in Computer Science, page 339-353. Springer, (2007)Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies., , , , , and . ICS, page 207-217. ACM, (2018)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , and . International Conference on Supercomputing, page 12-19. ACM, (1997)Software trace cache., , , , and . International Conference on Supercomputing, page 119-126. ACM, (1999)