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Time synchronization on SP1 and SP2 parallel systems., and . IPPS, page 666-672. IEEE Computer Society, (1995)Address tracing of parallel systems via TRAPEDS., , and . Microprocessors and Microsystems - Embedded Hardware Design, 16 (5): 249-261 (1992)Analysis of Hypercube Cache Performance Using Address Traces Generated by TRAPEDS., and . ICPP (1), page 33-40. Pennsylvania State University Press, (1989)Implementing Multidestination Worms in Switch-Based Parallel Systems: Architectural Alternatives and Their Impact., , and . IEEE Trans. Parallel Distrib. Syst., 11 (8): 794-812 (2000)Efficient Broadcast and Multicast on Multistage Interconnection Networks Using Multiport Encoding., , and . IEEE Trans. Parallel Distrib. Syst., 9 (10): 1004-1028 (1998)Architectural Support for Efficient Multicasting in Irregular Networks., , , and . IEEE Trans. Parallel Distrib. Syst., 12 (5): 489-513 (2001)CASS Introduction., , and . IPDPS Workshops, page 716-717. IEEE, (2011)HIPIQS: A High-Performance Switch Architecture Using Input Queuing., , and . IEEE Trans. Parallel Distrib. Syst., 13 (3): 275-289 (2002)The SP2 High-Performance Switch., , , , , , , , , and 3 other author(s). IBM Systems Journal, 34 (2): 185-204 (1995)Sp2 high-performance switch architecture., and . Hot Interconnects, page 190-195. IEEE, (1994)