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Disambiguation of "Gambardella, Giulio"

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An area-efficient 2-D convolution implementation on FPGA for space applications.

, , , , , and . IDT, page 88-92. IEEE, (2011)

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Other publications of authors with the same name

Validation & Verification of an EDA automated synthesis tool., , , , and . IDT, page 48-52. IEEE, (2011)MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches., , , , and . Asian Test Symposium, page 401-406. IEEE Computer Society, (2011)Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic., , , , , , , and . ARC, volume 10824 of Lecture Notes in Computer Science, page 29-42. Springer, (2018)FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs., , , , , and . FPL, page 89-96. IEEE Computer Society, (2018)Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks., , , , and . ICONIP (2), volume 10635 of Lecture Notes in Computer Science, page 393-404. Springer, (2017)ZipStream: Improving dependability in dynamic partial reconfiguration., , , , , and . IDT, page 1-6. IEEE, (2013)An area-efficient 2-D convolution implementation on FPGA for space applications., , , , , and . IDT, page 88-92. IEEE, (2011)FEMIP: A high performance FPGA-based features extractor & matcher for space applications., , , , , and . FPL, page 1-4. IEEE, (2013)FINN: A Framework for Fast, Scalable Binarized Neural Network Inference., , , , , , and . FPGA, page 65-74. ACM, (2017)Inference of quantized neural networks on heterogeneous all-programmable devices., , , and . DATE, page 833-838. IEEE, (2018)