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Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems.

, , , , , and . J. Low Power Electronics, 4 (3): 385-391 (2008)

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Guest Editorial., and . J. Electronic Testing, 20 (4): 331-332 (2004)Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip., , , , , and . J. Electronic Testing, 21 (4): 349-363 (2005)A dynamic TDMA-based sleep scheduling to minimize WSN energy consumption., , , , , and . ICNSC, page 1-6. IEEE, (2016)Signal Integrity Enhancement in Digital Circuits., , , , , , , and . IEEE Design & Test of Computers, 25 (5): 452-461 (2008)Time Management for Low-Power Design of Digital Systems., , , , , , and . J. Low Power Electronics, 4 (3): 410-419 (2008)An Approach for Designing Total-Dose Tolerant MCMs Based on Current Monitoring., , and . ITC, page 345-354. IEEE Computer Society, (1995)Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG., , , , , , , , , and 1 other author(s). LATS, page 1-6. IEEE Computer Society, (2015)A New Approach to Guarantee Critical Task Schedulability in TDMA-Based Bus Access of Multicore Architecture., , , , , , and . LATS, page 1-6. IEEE, (2019)On-chip aging sensor to monitor NBTI effect in nano-scale SRAM., , , and . DDECS, page 354-359. IEEE, (2012)Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems., , and . Asian Test Symposium, page 224-229. IEEE Computer Society, (2002)