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Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching., , , , and . IEEE Micro, 28 (1): 91-98 (2008)Accelerating Critical Section Execution with Asymmetric Multicore Architectures., , , and . IEEE Micro, 30 (1): 60-70 (2010)Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs., , and . ASPLOS, page 277-286. ACM, (2008)ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates., , and . ISCA, page 72-83. ACM, (2013)Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM., , , , , and . HPCA, page 568-580. IEEE Computer Society, (2016)DICE: Compressing DRAM Caches for Bandwidth and Capacity., , and . ISCA, page 627-638. ACM, (2017)ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction., , , and . ISCA, page 328-339. IEEE Computer Society, (2018)FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion., , , and . ISCA, page 321-332. IEEE Computer Society, (2012)Adaptive insertion policies for high performance caching., , , , and . ISCA, page 381-391. ACM, (2007)Lookout for Zombies: Mitigating Flush+Reload Attack on Shared Caches by Monitoring Invalidated Lines., and . CoRR, (2019)