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Disambiguation of "Arimoto, Kazutami"

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A smart low power R-R-I heartbeat monitor system with contactless UWB sensor.

, , , , , , and . ISOCC, page 63-64. IEEE, (2017)

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Other publications of authors with the same name

A Scalable Massively Parallel Processor for Real-Time Image Processing., , , , , , , , , and 9 other author(s). J. Solid-State Circuits, 46 (10): 2363-2373 (2011)A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros., , , , , , , , , and 2 other author(s). IEICE Transactions, 88-C (10): 2020-2027 (2005)A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM., , , and . CICC, page 451-454. IEEE, (2005)Test Pattern Considerations for Fault Tolerant High Density DRAM., , , , , and . ITC, page 451-455. IEEE Computer Society, (1985)Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor., , , , and . ISMVL, page 43. IEEE Computer Society, (2007)A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs., , , , , and . J. Solid-State Circuits, 42 (11): 2611-2619 (2007)Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications., , , , , , , , , and 6 other author(s). J. Solid-State Circuits, 44 (8): 2251-2259 (2009)A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory., , , , , , , and . J. Solid-State Circuits, 42 (4): 853-861 (2007)An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs., , , , , , , , , and 4 other author(s). ISSCC, page 266-268. IEEE, (2011)Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters., , , , , , and . IEEE Design & Test of Computers, 10 (2): 6-12 (1993)