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Evaluating Run-Time Techniques for Leakage Power Reduction.

, , , and . VLSI Design, page 31-38. IEEE Computer Society, (2002)

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Leakage-Aware Interconnect for On-Chip Network., , , and . DATE, page 230-231. IEEE Computer Society, (2005)Leakage-Aware Interconnect for On-Chip Network, , , and . CoRR, (2007)Implications of technology scaling on leakage reduction techniques., , , and . DAC, page 187-190. ACM, (2003)Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty., , , and . VLSI Design, page 374-379. IEEE Computer Society, (2005)Reducing leakage energy in FPGAs using region-constrained placement., , , , , and . FPGA, page 51-58. ACM, (2004)ChipPower: an architecture-level leakage simulator., , , , and . SoCC, page 395-398. IEEE, (2004)Leakage Energy Management in Cache Hierarchies., , , , , , and . IEEE PACT, page 131-140. IEEE Computer Society, (2002)Managing Leakage Energy in Cache Hierarchies., , , , , , and . J. Instruction-Level Parallelism, (2003)Three-Dimensional Cache Design Exploration Using 3DCacti., , , and . ICCD, page 519-524. IEEE Computer Society, (2005)Reducing dynamic and leakage energy in VLIW architectures., , , , , and . ACM Trans. Embedded Comput. Syst., 5 (1): 1-28 (2006)