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Disambiguation of "Verma, Ajay K."

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Hybrid LZA: a near optimal implementation of the leading zero anticipator.

, , , and . ASP-DAC, page 203-209. IEEE, (2009)

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K. Stahl

K. Gaiser

K. Lindow

Prabal Singh Verma University of Stuttgart

Chinmay Ajay Pabshettiwar University of Stuttgart

 

Other publications of authors with the same name

Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic., , , , and . FPL, page 19-24. IEEE Computer Society, (2010)Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits., , and . DAC, page 404-409. IEEE, (2007)Rethinking custom ISE identification: a new processor-agnostic method., , and . CASES, page 125-134. ACM, (2007)Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs., , , , , , , , , and . TRETS, 2 (2): 13:1-13:36 (2009)Optimistic chordal coloring: a coalescing heuristic for SSA form programs., , and . Design Autom. for Emb. Sys., 13 (1-2): 115-137 (2009)Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography., , , , and . DATE, page 218-223. European Design and Automation Association, Leuven, Belgium, (2006)Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design., , and . DATE, page 1250-1255. ACM, (2008)Increased Systolic Blood Pressure driven Skeletal Muscle activation Following Stroke: A causality analysis., , , , , , and . CinC, www.cinc.org, (2016)Analysis of causal cardio-postural interaction under orthostatic stress using convergent cross mapping., , , , and . EMBC, page 2319-2322. IEEE, (2016)Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design., , and . ICCAD, page 172-179. IEEE Computer Society, (2007)