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Disambiguation of "Jou, Shyh-Jye"

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Mixed-VTH (MVT) CMOS circuit design for low power cell libraries.

, , , and . SoCC, page 181-184. IEEE, (2007)

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Juri Joussen University of Stuttgart

Tim Jourdan University of Stuttgart

Shyh-Giun Hofmann University of Stuttgart

 

Other publications of authors with the same name

Memory reduction ICFO estimation architecture for DVB-T., , and . ISCAS, IEEE, (2006)Correction to "Low complexity formant estimation adaptive feedback cancellation for hearing aids using pitch based processing"., , , , , and . IEEE/ACM Trans. Audio, Speech & Language Processing, 22 (12): 2256 (2014)Design and analysis of digital data recovery circuits using oversampling., , , and . IET Circuits, Devices & Systems, 1 (1): 95-101 (2007)A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control., , , , , , , , , and 3 other author(s). SoCC, page 110-115. IEEE, (2013)Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver., , , , , and . IEEE Trans. VLSI Syst., 24 (11): 3323-3333 (2016)Error-resilient sequential cells with successive time borrowing for stochastic computing., , , , , and . ICASSP, page 6545-6549. IEEE, (2016)An IDDQ Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan Environment., , and . ITC, page 670-676. IEEE Computer Society, (1994)A 50 Gb/s Adaptive Dual Data-Paths NS-EICL ADFE with 50 Parallelisms for 2-PAM Systems., , , and . ISCAS, page 1-5. IEEE, (2019)Introduction to the Special Section on the 2007 Asian Solid-State Circuits Conference (A-SSCC'07)., and . J. Solid-State Circuits, 43 (11): 2352-2353 (2008)A pitch based VAD adopting quasi-ANSI 1/3 octave filter bank with 11.3 ms latency for monosyllable hearing aids., , and . SiPS, page 48-53. IEEE, (2013)