PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Banerjee, P."

Author of the publication

copydeleteadd this publication to your clipboard
Ensemble-Based Algorithm for Synchrophasor Data Anomaly Detection.

, , , , and . IEEE Trans. Smart Grid, 10 (3): 2979-2988 (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sayan Banerjee University of Stuttgart

P. Hommel

P. Abegglen

P. Krasteva

P. E. Bl\"ochl

 

Other publications of authors with the same name

An Effective Dynamic Current Phasor Estimator for Synchrophasor Measurements., and . IEEE Trans. Instrumentation and Measurement, 64 (3): 625-637 (2015)Knowledge-based facility planning: a review and a framework., and . J. Intelligent Manufacturing, 5 (6): 399-409 (1994)Quantitative Analysis of Histopathological Features of Precancerous Lesion and Condition Using Image Processing Technique., , , , , , , and . CBMS, page 231-236. IEEE Computer Society, (2006)The Importance of Technical Capabilities in E-Governance: Development and Validation of a Framework., , and . AMCIS, page 288. Association for Information Systems, (2010)Bag-of-features HMMs for segmentation-free Bangla word spotting., , , , and . MOCR@ICDAR, page 5:1-5:5. ACM, (2013)Effect of Scintillation on Timing Applications of GPS in Indian Subcontinent., , and . IEEE Trans. Instrumentation and Measurement, 56 (5): 1596-1600 (2007)A Subspace-Based Dynamic Phasor Estimator for Synchrophasor Application., and . IEEE Trans. Instrumentation and Measurement, 61 (9): 2436-2445 (2012)Parallel construction algorithms for BDDs., and . ISCAS (1), page 318-322. IEEE, (1999)Ensemble-Based Algorithm for Synchrophasor Data Anomaly Detection., , , , and . IEEE Trans. Smart Grid, 10 (3): 2979-2988 (2019)Remote PMU Testing using Low-cost FPGA Platform and PPA following IEEE TSS., , , , and . IAS, page 1-7. IEEE, (2019)