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Disambiguation of "Dalt, Nicola Da"

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Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters.

, , , and . ESSCIRC, page 392-395. IEEE, (2015)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Nicola Fanton University of Stuttgart

Nicola Mrdovic University of Stuttgart

Nicola Schuckert University of Stuttgart

PD Dr. Nicola Mößner University of Stuttgart

Samir Darouich University of Stuttgart

Replication Data for: Transferable Anisotropic Mie Potential Force Field for Alkanediols, , , and . Dataset, (2024)Related to: Fleck, Maximilian; Darouich, Samir; Hansen, Niels; Gross, Joachim (2024): Transferable Anisotropic Mie Potential Force Field for Alkanediols. In: The Journal of Physical Chemistry B, 128, 4792-4801. doi: 10.1021/acs.jpcb.4c00962.
 

Other publications of authors with the same name

ES3: High-speed communications on 4 wheels: What's in your next car?, and . ISSCC, page 515. IEEE, (2013)Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters., , , and . ESSCIRC, page 392-395. IEEE, (2015)Effect of jitter on asynchronous sampling with finite number of samples.. IEEE Trans. on Circuits and Systems, 51-II (12): 660-664 (2004)digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture., , , , and . J. Solid-State Circuits, 48 (12): 3134-3145 (2013)Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs., , , , , and . IEEE Trans. on Circuits and Systems, 55-I (6): 1628-1638 (2008)A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider., , , , and . ISSCC, page 356-357. IEEE, (2013)A 0.06 mm 2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS., , , , , and . J. Solid-State Circuits, 45 (7): 1295-1304 (2010)An all-digital PLL using random modulation for SSC generation in 65nm CMOS., , and . ISSCC, page 252-253. IEEE, (2013)Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation.. IEEE Trans. on Circuits and Systems, 55-I (11): 3663-3675 (2008)Jitter Noise of Sampled Multitone Signals., and . IEEE Trans. on Circuits and Systems, 58-II (10): 652-656 (2011)