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Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations.

S. Yin, S. Venkataramanaiah, G. Chen, R. Krishnamurthy, Y. Cao, C. Chakrabarti, and J. sun Seo. BioCAS, page 1-5. IEEE, (2017)

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Inference engine benchmarking across technological platforms from CMOS to RRAM.X. Peng, M. Kim, X. Sun, S. Yin, T. Rakshit, R. Hatcher, J. Kittl, J. sun Seo, and S. Yu. MEMSYS, page 471-479. ACM, (2019)Automatic Compiler Based FPGA Accelerator for CNN Training.S. Venkataramanaiah, Y. Ma, S. Yin, E. Nurvitadhi, A. Dasu, Y. Cao, and J. sun Seo. FPL, page 166-172. IEEE, (2019)Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning.S. Yin, J. sun Seo, Y. Kim, X. Han, H. Barnaby, S. Yu, Y. Luo, W. He, X. Sun, and J. Kim. IEEE Micro, 39 (6): 54-63 (2019)Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations.S. Yin, S. Venkataramanaiah, G. Chen, R. Krishnamurthy, Y. Cao, C. Chakrabarti, and J. sun Seo. BioCAS, page 1-5. IEEE, (2017)Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression.S. Yin, G. Srivastava, S. Venkataramanaiah, C. Chakrabarti, V. Berisha, and J. sun Seo. CoRR, (2018)K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM.J. Saikia, S. Yin, Z. Jiang, M. Seok, and J. sun Seo. ISLPED, page 1-6. IEEE, (2019)Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data.Y. Wang, S. Yin, M. Jun, X. Li, L. Pileggi, T. Mukherjee, and R. Negi. ASP-DAC, page 441-446. IEEE, (2015)Phase Noise Impairment and Environment-Adaptable Fast (EAF) Optimization for Programming of Reconfigurable Radio Frequency (RF) Receivers.M. Jun, R. Negi, S. Yin, F. Wang, M. Sunny, T. Mukherjee, and X. Li. GLOBECOM, page 1-6. IEEE, (2015)Re-thinking polynomial optimization: Efficient programming of reconfigurable radio frequency (RF) systems by convexification.F. Wang, S. Yin, M. Jun, X. Li, T. Mukherjee, R. Negi, and L. Pileggi. ASP-DAC, page 545-550. IEEE, (2016)Designing ECG-based physical unclonable function for security of wearable devices.S. Yin, C. Bae, S. Kim, and J. sun Seo. EMBC, page 3509-3512. IEEE, (2017)

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Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations.

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Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations.