PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Srinivasan, Suresh"

Author of the publication

copydeleteadd this publication to your clipboard
Tracking meaning over time in the UMLS Metathesaurus.

, , , , , and . AMIA, AMIA, (2002)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Prashanth Srinivasan University of Stuttgart

 

Other publications of authors with the same name

Variation Aware Placement for FPGAs., and . ISVLSI, page 422-423. IEEE Computer Society, (2006)Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures., , and . DATE, page 218-223. IEEE Computer Society, (2005)Adding neuronames to the UMLS metathesaurus., and . Neuroinformatics, 1 (1): 61-63 (2003)Exploring architectural solutions for energy optimisations in bus-based system-on-chip., , , , , and . IET Computers & Digital Techniques, 2 (5): 347-354 (2008)Process Variation Aware Parallelization Strategies for MPSoCs., , and . SoCC, page 179-182. IEEE, (2006)2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors., , , , , , , , and . IEEE J. Solid State Circuits, 47 (11): 2807-2821 (2012)FPGA routing architecture analysis under variations., , , and . ICCD, page 152-157. IEEE, (2007)18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS., , , , , , , , , and . ESSCIRC, page 210-213. IEEE, (2010)Simultaneous memory and bus partitioning for SoC architectures., , , , and . SoCC, page 125-128. IEEE, (2005)Discovering missed synonymy in a large concept-oriented Metathesaurus., and . AMIA, AMIA, (2000)