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OSPREY: Implementation of Memory Consistency Models for Cache Coherence Protocols involving Invalidation-Free Data Access.

, , , and . PACT, page 392-405. IEEE Computer Society, (2015)

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Improving yield and reliability of chip multiprocessors., , and . DATE, page 490-495. IEEE, (2009)Hardware/software co-design architecture for thermal management of chip multiprocessors., and . DATE, page 952-957. IEEE, (2009)Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtime., and . IET Circuits, Devices & Systems, 6 (5): 355-365 (2012)The Execution Migration Machine: Directoryless Shared-Memory Architecture., , , and . IEEE Computer, 48 (9): 50-59 (2015)CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on Futuristic Multicores., , , and . IISWC, page 44-55. IEEE Computer Society, (2015)Efficient parallel packet processing using a shared memory many-core processor with hardware support to accelerate communication., , , and . NAS, page 122-129. IEEE Computer Society, (2015)Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores., , , , and . PACT, page 121-130. IEEE Computer Society, (2011)OSPREY: Implementation of Memory Consistency Models for Cache Coherence Protocols involving Invalidation-Free Data Access., , , and . PACT, page 392-405. IEEE Computer Society, (2015)A low-overhead dynamic optimization framework for multicores., , , and . PACT, page 467-468. ACM, (2012)Deadlock-free fine-grained thread migration., , , , and . NOCS, page 33-40. ACM/IEEE Computer Society, (2011)