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Challenges and Promising Results in NoC Prototyping Using FPGAs., , , , , , and . IEEE Micro, 27 (5): 86-95 (2007)Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures, and . Lecture Notes in Electrical Engineering Springer, (2013)Virtual Channels Planning for Networks-on-Chip., , and . ISQED, page 879-884. IEEE Computer Society, (2007)Can systems extend to polymer? SoP architecture design and challenges., , and . SoCC, page 203-208. IEEE, (2015)OS-level power minimization under tight performance constraints in general purpose systems., , , , , , and . ISLPED, page 321-326. IEEE/ACM, (2011)Multi-product floorplan and uncore design framework for chip multiprocessors., , , , and . SLIP, page 1-7. IEEE, (2015)Making unreliable Chem-FET sensors smart via soft calibration., , , , and . ISQED, page 456-461. IEEE, (2016)Exploration of Memory and Cluster Modes in Directory-Based Many-Core CMPs., , , and . NOCS, page 2:1-2:8. IEEE, (2018)Online learning for adaptive optimization of heterogeneous SoCs., , , and . ICCAD, page 61. ACM, (2018)Variation-adaptive feedback control for networks-on-chip with multiple clock domains., , and . DAC, page 614-619. ACM, (2008)