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Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information.

, , and . DATE, page 10770-10777. IEEE Computer Society, (2003)

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Technologienahe Retimingverfahren zur Optimierung synchroner digitaler Schaltungen.. Technical University Munich, (2003)Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs., , , and . ACM Trans. Design Autom. Electr. Syst., 4 (3): 313-350 (1999)Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information., , and . DATE, page 10770-10777. IEEE Computer Society, (2003)A Practical Approach to Multiple-Class Retiming., , , and . DAC, page 237-242. ACM Press, (1999)An Implicit Algorithm for Support Minimization during Functional Decomposition., , and . ED&TC, page 412-419. IEEE Computer Society, (1996)Retiming Sequential Circuits with Multiple Register Classes., and . DATE, page 650-. IEEE Computer Society / ACM, (1999)Performance-Directed Technology-Mapping for LUT-Based FPGAs - What Role Do Decomposition and Covering Play?, , and . FPL, volume 1142 of Lecture Notes in Computer Science, page 14-23. Springer, (1996)Computing support-minimal subfunctions during functional decomposition., , and . IEEE Trans. VLSI Syst., 6 (3): 354-363 (1998)Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm., , and . DAC, page 54-59. ACM Press, (1995)A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs., , and . DAC, page 730-733. ACM Press, (1996)