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Optimization for the Intel® Itanium ®Architectur Register Stack.

, , , and . CGO, page 115-124. IEEE Computer Society, (2003)

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Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture., , , , , and . SIGMETRICS, page 361-362. ACM, (2007)The Intel IA-64 Compiler Code Generator., , , , , , and . IEEE Micro, 20 (5): 44-53 (2000)AstroLIT: enabling simulation-based microarchitecture comparison between Intel® and Transmeta designs., , , , , , , , and . Conf. Computing Frontiers, page 21. ACM, (2011)Optimization for the Intel® Itanium ®Architectur Register Stack., , , and . CGO, page 115-124. IEEE Computer Society, (2003)Compiler Optimizations for Transaction Processing Workloads on Itanium® Linux Systems., , , , , and . MICRO, page 294-303. IEEE Computer Society, (2004)Performance Characterization of Itanium® 2-Based Montecito Processor., , , , , , and . SPEC Benchmark Workshop, volume 5419 of Lecture Notes in Computer Science, page 36-56. Springer, (2009)Strategies for Predicate-Aware Register Allocation.. CC, volume 6011 of Lecture Notes in Computer Science, page 185-204. Springer, (2010)The compiler as a validation and evaluation tool., , and . Electron. Notes Theor. Comput. Sci., 82 (2): 443-460 (2003)Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors., , , , , , and . Interaction between Compilers and Computer Architectures, page 57-67. IEEE Computer Society, (2002)Post-Pass Binary Adaptation for Software-Based Speculative Precomputation., , , , , and . PLDI, page 117-128. ACM, (2002)