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Exploiting transaction level models for observability-aware post-silicon test generation.

, , and . DATE, page 1477-1480. IEEE, (2016)

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Functional Coverage Driven Test Generation for Validation of Pipelined Processors., and . DATE, page 678-683. IEEE Computer Society, (2005)Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study., , , and . MTV, page 33-36. IEEE Computer Society, (2006)Dynamic Selection of Trace Signals for Post-Silicon Debug., , , , and . MTV, page 62-67. IEEE Computer Society, (2013)Functional verification of programmable embedded architectures - a top-down approach., and . Springer, (2005)Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language., , , and . VLSI Design, page 70-75. IEEE Computer Society, (2001)Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures., , and . VLSI Design, page 49-54. IEEE Computer Society, (2013)Energy-aware dynamic reconfiguration algorithms for real-time multitasking systems., , and . SUSCOM, 1 (1): 35-45 (2011)Directed test generation for validation of multicore architectures., and . ACM Trans. Design Autom. Electr. Syst., 17 (3): 24:1-24:21 (2012)Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation., , and . ACM Trans. Embedded Comput. Syst., 8 (3): 20:1-20:27 (2009)Vulnerability-Aware Energy Optimization for Reconfigurable Caches in Multitasking Systems., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 38 (5): 809-821 (2019)