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Disambiguation of "Mathieu, Yves"

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Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology.

, , , , , , , and . DSD, page 508-515. IEEE Computer Society, (2018)

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Yves Klett

 

Other publications of authors with the same name

DPL on Stratix II FPGA: What to Expect?., , , , , and . ReConFig, page 243-248. IEEE Computer Society, (2009)A dual threshold voltage technique for glitch minimization., , and . ICECS, page 444-447. IEEE, (2012)High Efficiency Reconfigurable Cache for Image Processing., , and . ERSA, page 226-232. CSREA Press, (2009)CMOS Structures Suitable for Secured Hardware., , , , and . DATE, page 1414-1415. IEEE Computer Society, (2004)Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography., , , , and . Int. J. Reconfig. Comp., (2012)Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology., , and . CoRR, (2016)Cache-Timing Attacks Still Threaten IoT Devices., , , , , , and . C2SI, volume 11445 of Lecture Notes in Computer Science, page 13-30. Springer, (2019)Exploration of 3D grid caching strategies for ray-shooting., , , , and . J. Real-Time Image Processing, 7 (1): 3-19 (2012)Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security., , , , , and . FPL, page 1-4. IEEE, (2014)Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs., , , , and . SSIRI, page 16-23. IEEE Computer Society, (2008)