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Longest-path selection for delay test under process variation.

, , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 24 (12): 1924-1929 (2005)

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A Statistical Fault Coverage Metric for Realistic Path Delay Faults., , , , , and . VTS, page 37-42. IEEE Computer Society, (2004)Longest path selection for delay test under process variation., , , , and . ASP-DAC, page 98-103. IEEE Computer Society, (2004)Minimum moment Steiner trees., and . SODA, page 488-495. SIAM, (2004)Macro Model of Advanced Devices for Parasitic Extraction., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (10): 1721-1729 (2016)A vector-based approach for power supply noise analysis in test compaction., , , , , and . ITC, page 10. IEEE Computer Society, (2005)Longest-path selection for delay test under process variation., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 24 (12): 1924-1929 (2005)A circuit level fault model for resistive bridges., , , , and . ACM Trans. Design Autom. Electr. Syst., 8 (4): 546-559 (2003)K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits., , , , , , and . ITC, page 223-231. IEEE Computer Society, (2004)A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide., , , , and . MTV, page 97-102. IEEE Computer Society, (2004)PARADE: PARAmetric Delay Evaluation under Process Variation., , , , and . ISQED, page 276-280. IEEE Computer Society, (2004)