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Disambiguation of "Andreani, Pietro"

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A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing.

, , , and . ISCAS, page 169-172. IEEE, (2013)

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Other publications of authors with the same name

A 1-1 MASH 2-D vernier time-to-digital converter with 2nd-order noise shaping., and . ISCAS, page 1324-1327. IEEE, (2014)A 57-dB image band rejection CMOS G/sub m/-C polyphase filter with automatic frequency tuning for Bluetooth., , and . ISCAS (5), page 169-172. IEEE, (2002)A 6.7-to-9.2GHz 55nm CMOS hybrid Class-B/Class-C cellular TX VCO., , and . ISSCC, page 354-356. IEEE, (2012)Low-phase-noise 3.4-4.5 GHz dynamic-bias class-C CMOS VCOs with a FoM of 191 dBc/Hz., and . ESSCIRC, page 406-409. IEEE, (2012)A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs., , and . ESSCIRC, page 459-462. IEEE, (2011)A Class-D CMOS DCO with an on-chip LDO., , and . ESSCIRC, page 335-338. IEEE, (2014)A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing., , , and . ISCAS, page 169-172. IEEE, (2013)A 65 nm CMOS Wideband Radio Receiver With ΔΣ-Based A/D-Converting Channel-Select Filters., , , , , , and . J. Solid-State Circuits, 51 (7): 1566-1578 (2016)A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers., , , and . J. Solid-State Circuits, 49 (3): 646-656 (2014)New Associate Editors., , and . J. Solid-State Circuits, 51 (5): 1063 (2016)