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Architecture and Implementation of a Reduced EPIC Processor.

J. Gao, M. Zhang, Z. Xing, and C. Feng. IEICE Transactions, 96-D (1): 9-18 (2013)

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Xing Yang University of Stuttgart

Other publications of authors with the same name

UniMESH: The light-weight unidirectional channel Network-on-Chip in 2D mesh topology.F. Wang, X. Tang, Z. Xing, and H. Liu. CONIELECOMP, page 104-109. IEEE, (2015)A 64-bit stream processor architecture for scientific applications.X. Yang, X. Yan, Z. Xing, Y. Deng, J. Jiang, and Y. Zhang. ISCA, page 210-219. ACM, (2007)QRD Architecture Using the Modified ILMGS Algorithm for MIMO Systems.C. Liu, C. Tang, Z. Xing, L. Yuan, Y. Wang, L. Chen, Y. Zhang, S. Xiang, W. Zhao, X. Hu and 1 other author(s). WICON, volume 214 of Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, page 164-178. Springer, (2016)An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors.C. Zhang, H. Zhou, M. Zhang, and Z. Xing. Asia-Pacific Computer Systems Architecture Conference, volume 4186 of Lecture Notes in Computer Science, page 588-594. Springer, (2006)A Delay Model of Two-Cycle NoC Router in 2D-Mesh Network.S. Qi, J. Li, Z. Xing, X. Jia, and M. Zhang. ISVLSI, page 316-320. IEEE Computer Society, (2010)Characterizing Time-Varying Behavior and Predictability of Cache AVF.Y. Cheng, Y. Wang, Z. Xing, and M. Zhang. INCoS, page 720-725. IEEE Computer Society, (2011)DIPP - An LLC Replacement Policy for On-chip Dynamic Heterogeneous Multi-core Architecture.Y. Zhang, Z. Xing, and X. Ma. ICYCSEE, volume 503 of Communications in Computer and Information Science, page 386-397. Springer, (2015)Flexible Virtual Channel Power-Gating for High-Throughput and Low-Power Network-on-Chip.F. Wang, X. Tang, Q. Wang, Z. Xing, and H. Liu. DSD, page 504-511. IEEE Computer Society, (2014)Algorithm and Architecture for Path Metric Aided Bit-Flipping Decoding of Polar Codes.Y. Wang, L. Chen, Q. Wang, Y. Zhang, and Z. Xing. WCNC, page 1-6. IEEE, (2019)Reconfigurable pseudo-NMOS-like logic with hybrid MOS and single-electron transistors.X. Chen, Z. Xing, B. Sui, and S. Ni. IEICE Electronic Express, 10 (20): 20130697 (2013)

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Disambiguation of "Xing, Zuocheng"

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Architecture and Implementation of a Reduced EPIC Processor.

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Xing Yang University of Stuttgart

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Xing Yang University of Stuttgart

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Architecture and Implementation of a Reduced EPIC Processor.