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Fast Lithographic Mask Optimization Considering Process Variation.

, , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (8): 1345-1357 (2016)

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MR: a new framework for multilevel full-chip routing., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 23 (5): 793-800 (2004)TCG-S: orthogonal coupling of P/sup */-admissible representations for general floorplans., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 23 (6): 968-980 (2004)Matching-based algorithm for FPGA channel segmentation design., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 20 (6): 784-791 (2001)RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction., , and . ISCAS (4), page 4134-4137. IEEE, (2005)Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability., , , , , and . ASP-DAC, page 238-243. IEEE Computer Society, (2007)Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation., , , and . VLSI Design, 2002 (3): 587-594 (2002)Analytical solution of Poisson's equation and its application to VLSI global placement., , , and . ICCAD, page 2. ACM, (2018)A multithreaded initial detailed routing algorithm considering global routing guides., , , , and . ICCAD, page 82. ACM, (2018)3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design., , , , , , and . ICME, page 9. IEEE Computer Society, (2007)A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing., , , , and . DAC, page 217. ACM, (2019)