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Disambiguation of "Sze, Cliff C. N."

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Timing-Driven Interconnect Synthesis.

, , and . Handbook of Algorithms for Physical Design Automation, Auerbach Publications, (2008)

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Konstantin Szengel University of Stuttgart

C. Traut

C. Honold

Dr. Quynh Ngo University of Stuttgart

Dataset for NMF-based Analysis of Mobile Eye-Tracking Data, , , and . Dataset, (2024)Related to: Daniel Klötzl, Tim Krake, Frank Heyen, Michael Becher, Maurice Koch, Daniel Weiskopf, and Kuno Kurzhals. 2024. NMF-Based Analysis of Mobile Eye-Tracking Data. In 2024 Symposium on Eye Tracking Research and Applications (ETRA ’24), June 4-7, 2024, Glasgow, United Kingdom. ACM, New York, NY, USA, 9 pages. doi: 10.1145/3649902.3653518.

Jan-Philipp Negel

Thin-disk multipass amplifier for fs pulses delivering 400 W of average and 2.0 GW of peak power for linear polarization as well as 235 W and 1.2 GW for radial polarization, , , , , , , and . Applied Physics. B, Lasers and optics, 123 (5): 156 (2017)
 

Other publications of authors with the same name

Postgrid Clock Routing for High Performance Microprocessor Designs., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (2): 255-259 (2012)CATALYST: planning layer directives for effective design closure., , , , , and . DATE, page 1873-1878. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths., , , , and . ASP-DAC, page 350-355. IEEE, (2013)Porosity-aware buffered Steiner tree construction., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 23 (4): 517-526 (2004)Accurate estimation of global buffer delay within a floorplan., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (6): 1140-1145 (2006)Ultra-fast interconnect driven cell cloning for minimizing critical path delay., , , , , , and . ISPD, page 75-82. ACM, (2010)Cell Selection for High-Performance Designs in an Industrial Design Flow., , and . ISPD, page 65-72. ACM, (2016)ISPD 2010 high performance clock network synthesis contest: benchmark suite and results.. ISPD, page 143. ACM, (2010)Grid-to-ports clock routing for high performance microprocessor designs., , , and . ISPD, page 21-28. ACM, (2011)GLARE: global and local wiring aware routability evaluation., , , , , , , , , and . DAC, page 768-773. ACM, (2012)