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Design of STR level converters for SoCs using the multi-island dual-VDD design technique., , , and . ISCAS, IEEE, (2006)An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation., , , and . SoCC, page 5-10. IEEE, (2012)Energy-efficient RISC design with on-demand circuit-level timing speculation., , , , and . ASP-DAC, page 477-478. IEEE, (2012)A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS., , , , , , and . A-SSCC, page 361-364. IEEE, (2014)A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS., , , , , , , , , and 8 other author(s). ISSCC, page 158-159. IEEE, (2013)Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits., , , , , and . ISCAS, page 1572-1575. IEEE, (1995)Collaborative voltage scaling with online STA and variable-latency datapath., , , , , , , and . ACM Great Lakes Symposium on VLSI, page 347-352. ACM, (2010)PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems., , , , , and . SoCC, page 136-139. IEEE, (2014)Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells., , , , , , , , and . IEEE Trans. on Circuits and Systems, 61-II (12): 947-951 (2014)Energy-efficient real-time scheduling of multimedia tasks on multi-core processors., , , , and . SAC, page 258-262. ACM, (2010)