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Designing Chip-Level Nanophotonic Interconnection Networks., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (2): 137-153 (2012)Sub-threshold logic circuit design using feedback equalization., and . DATE, page 1-6. European Design and Automation Association, (2014)Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing., , and . IEEE Trans. VLSI Syst., 15 (9): 990-1002 (2007)Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization., and . IEEE Trans. VLSI Syst., 24 (3): 884-896 (2016)A Modeling and exploration framework for interconnect network design in the nanometer era., , and . NOCS, page 91. IEEE Computer Society, (2009)UMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs., , , , , , , , and . TACO, 13 (4): 35:1-35:25 (2016)CUDA optimized Neural Network predicts blood glucose control from quantified joint mobility and anthropometrics., , , and . CoRR, (2019)MGSim + MGMark: A Framework for Multi-GPU System Research., , , , , , , , , and 3 other author(s). CoRR, (2018)Reliable MLC NAND flash memories based on nonlinear t-error-correcting codes., , and . DSN, page 41-50. IEEE Computer Society, (2010)Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)., and . IEEE Trans. VLSI Syst., 13 (8): 899-910 (2005)