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Portable and scalable FPGA-based acceleration of a direct linear system solver.

, , and . TRETS, 5 (1): 6:1-6:26 (2012)

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Hard vs. Soft: The Central Question of Pre-Fabricated Silicon.. ISMVL, page 2-5. IEEE Computer Society, (2004)A Verilog RTL Synthesis Tool for Heterogeneous FPGAs., and . FPL, page 305-310. IEEE, (2005)Speed and area tradeoffs in cluster-based FPGA architectures., , and . IEEE Trans. VLSI Syst., 8 (1): 84-93 (2000)A novel and efficient routing architecture for multi-FPGA systems., and . IEEE Trans. VLSI Syst., 8 (1): 30-39 (2000)Parallel global routing for standard cells.. IEEE Trans. on CAD of Integrated Circuits and Systems, 9 (10): 1085-1095 (1990)A stochastic model to predict the routability of field-programmable gate arrays., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 12 (12): 1827-1838 (1993)A detailed router for field-programmable gate arrays., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 11 (5): 620-628 (1992)High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors., , and . FCCM, page 9-16. IEEE Computer Society, (2016)Fine-Grained Interconnect Synthesis., , and . TRETS, 9 (4): 31:1-31:22 (2016)VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling., , , , , , , and . TRETS, 4 (4): 32:1-32:23 (2011)