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Verification of Component Fault Trees Using Error Effect Simulations.

, , , , , and . IMBSA, volume 10437 of Lecture Notes in Computer Science, page 212-226. Springer, (2017)

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Dependable Multicore Architectures at Nanoscale: The View From Europe., , , , , , , , , and 4 other author(s). IEEE Design & Test, 32 (2): 17-28 (2015)Energy Efficient Driving and Operation Strategies Based on Situation Awareness and Reasoning., , , , , , , , and . it - Information Technology, 54 (1): 5-16 (2012)Synchronisationsanalyse zur Multi-Prozeß-Synthese.. Karlsruhe Institute of Technology, Germany, (2003)ESL power analysis of embedded processors for temperature and reliability estimations., , and . CODES+ISSS, page 239-248. ACM, (2009)Worst-case performance analysis of parallel, communicating software processes., , and . CODES, page 37-42. ACM, (2002)Dominator homomorphism based code matching for source-level simulation of embedded software., , and . CODES+ISSS, page 305-314. ACM, (2011)Attack Surface Modeling and Assessment for Penetration Testing of IoT System Designs., , , , and . DSD, page 177-181. IEEE Computer Society, (2018)Neues Konzept zur Steigerung der Zuverlässigkeit einer ARM-basierten Prozessorarchitektur unter Verwendung eines CGRAs., , , , , and . MBMV, page 46-58. Albert-Ludwigs-Universität Freiburg, (2016)Latency-Optimized Force-directed Process Mapping for MPSoC Architectures., , , and . MBMV, page 145-156. Verlag Dr. Kovac, (2012)Reliability assessment of safety-relevant automotive systems in a model-based design flow., , , , and . ASP-DAC, page 417-422. IEEE, (2013)