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Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes.

, , , , and . IOLTS, page 275-280. IEEE, (2018)

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FPGA accelerated multipliers over binary composite fields constructed via low hamming weight irreducible polynomials., , and . IET Computers & Digital Techniques, 2 (1): 6-11 (2008)A Configurable Ring-Oscillator-Based PUF for Xilinx FPGAs., , and . DSD, page 651-657. IEEE Computer Society, (2011)A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs., , and . FPL, page 1-8. IEEE, (2014)Evaluating the Potential for Hardware Acceleration of Four NTRU-Based Key Encapsulation Mechanisms Using Software/Hardware Codesign., , , and . PQCrypto, volume 11505 of Lecture Notes in Computer Science, page 23-43. Springer, (2019)High-Speed RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two., and . FCCM, page 93. IEEE Computer Society, (2016)DAGS: Reloaded Revisiting Dyadic Key Encapsulation., , , , , , , , , and 3 other author(s). IACR Cryptology ePrint Archive, (2018)Image processing library for reconfigurable computers (abstract only)., , , and . FPGA, page 276. ACM, (2005)Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware., and . AES Candidate Conference, page 40-54. National Institute of Standards and Technology,, (2000)High-speed FPGA Implementation of the NIST Round 1 Rainbow Signature Scheme., and . ReConFig, page 1-8. IEEE, (2018)Implementation of Elliptic Curve Cryptosystems on a reconfigurable computer., , , and . FPT, page 60-67. IEEE, (2003)