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KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs.

, , , , , and . TRETS, 11 (1): 2:1-2:22 (2018)

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A Hardware Gaussian Noise Generator for Channel Code Evaluation., , , and . FCCM, page 69-. IEEE Computer Society, (2003)Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform., , and . FCCM, page 3-12. IEEE Computer Society, (2002)A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design., , and . FCCM, page 275-276. IEEE Computer Society, (2006)Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory., , and . DATE, page 902-908. IEEE Computer Society, (2002)Improved diagnosis of realistic interconnect shorts., and . ED&TC, page 501-505. IEEE Computer Society, (1997)Partition-based exploration for reconfigurable JPEG designs., , and . DATE, page 886-889. IEEE, (2009)Run-Time Integration of Reconfigurable Video Processing Systems., , , and . IEEE Trans. VLSI Syst., 15 (9): 1003-1016 (2007)Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices., , and . IEEE Trans. VLSI Syst., 16 (6): 733-744 (2008)Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs., , and . IEEE Trans. VLSI Syst., 18 (3): 436-449 (2010)Hardware architectures for eigenvalue computation of real symmetric matrices., , and . IET Computers & Digital Techniques, 3 (1): 72-84 (2009)