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Disambiguation of "Jiang, Yingtao"

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A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures.

, , , and . Computers & Electrical Engineering, 35 (6): 846-855 (2009)

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Chenming Jiang University of Stuttgart

 

Other publications of authors with the same name

Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages., , and . The Journal of Supercomputing, 35 (1): 93-113 (2006)Multiple voltage synthesis scheme for low power design under timing and resource constraints., , and . Integrated Computer-Aided Engineering, 12 (4): 369-378 (2005)Macro-cell placement for analog physical designs using a hybrid genetic algorithm with simulated annealing., , , , and . Integrated Computer-Aided Engineering, 12 (4): 379-396 (2005)Placement-Directed Behavioral Synthesis Scheme for Simultaneous Scheduling Binding and Partitioning with Resources Operating at Multiple Voltages., , , , and . I. J. Comput. Appl., 14 (2): 92-98 (2007)An efficient protocol with synchronization accelerator for multi-processor embedded systems., , , , , , and . Parallel Computing, 39 (9): 461-474 (2013)On an efficient NoC multicasting scheme in support of multiple applications running on irregular sub-networks., , , and . Microprocessors and Microsystems - Embedded Hardware Design, 35 (2): 119-129 (2011)Markov Reliability Modeling of Star Networks., , and . PDPTA, page 137-143. CSREA Press, (2007)Scheduling and Optimal Voltage Selection with Multiple Supply Voltages under Resource Constraints., , and . VLSI, page 272-278. CSREA Press, (2003)EECCP: an energy-efficient coverage- and connectivity preserving algorithm under border effects in wireless sensor networks., , , , and . WTS, page 310-315. IEEE, (2008)A RDT-Based Interconnection Network for Scalable Network-on-Chip Designs., , , and . ITCC (2), page 723-728. IEEE Computer Society, (2005)isbn: 0-7695-2315-3.