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Disambiguation of "U, Seng-Pan"

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A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity.

, , , , , and . APCCAS, page 33-36. IEEE, (2012)

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U. Schleinkofer

Qi Pan University of Stuttgart

Karthik Pandaram University of Stuttgart

Mehdiye Panzehir University of Stuttgart

Jiaxin Pan University of Stuttgart

 

Other publications of authors with the same name

Quantitative noise analysis of jitter-induced nonuniformly sampled-and-held signals., , and . ICASSP (6), page 253-256. IEEE, (2003)A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems., , and . ISCAS (1), page 320-323. IEEE, (2001)Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity., , and . ISCAS (2), page 57-60. IEEE, (1999)Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output., , , and . ISCAS (1), page 129-132. IEEE, (2003)A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems., , and . ISCAS (1), page 369-372. IEEE, (2004)A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC., , , and . ISCAS, page 1947-1950. IEEE, (2007)A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation., , , , and . IEEE Trans. on Circuits and Systems, 63-II (7): 683-687 (2016)A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC., , , , , and . J. Solid-State Circuits, 48 (8): 1783-1794 (2013)Quick and cost-efficient A/D converter static characterization using low-precision testing signal., , , and . Microelectronics Journal, (2018)A digital PWM controlled KY step-up converter based on frequency domain ΣΔ ADC., , , , , , , and . ISIE, page 561-564. IEEE, (2017)