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Disambiguation of "DeMara, Ronald F."

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Activity-Based Resource Allocation for Motion Estimation Engines.

, , , and . Journal of Circuits, Systems, and Computers, 24 (1): 1550004:1-1550004:32 (2015)

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F. Dörr

F. Laufer

F. Rusitschka

F. Perni

F. D{\"o}rr

 

Other publications of authors with the same name

Guest Editorial: IEEE Transactions on Computers Special Section on Emerging Non-Volatile Memory Technologies: From Devices to Architectures and Systems., , , and . IEEE Trans. Computers, 68 (8): 1111-1113 (2019)Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration., , , and . ACM Trans. Embedded Comput. Syst., 9 (1): 9:1-9:18 (2009)Progress in autonomous fault recovery of field programmable gate arrays., , and . ACM Comput. Surv., 43 (4): 31:1-31:30 (2011)Composable Probabilistic Inference Networks Using MRAM-based Stochastic Neurons., , , and . CoRR, (2018)Data-partitioning using the Hilbert space filling curves: Effect on the speed of convergence of Fuzzy ARTMAP for large database problems., , , and . Neural Networks, 18 (7): 967-984 (2005)Optimization of NULL convention self-timed circuits., , , , and . Integration, 37 (3): 135-165 (2004)Intrinsic evolvable hardware platform for digital circuit design and repair using genetic algorithms., and . Appl. Soft Comput., 12 (8): 2470-2480 (2012)Communication Pattern Based Methodology for Performance Analysis of Termination Detection Schemes., and . ICPADS, page 535-541. IEEE Computer Society, (2002)Scalable FPGA Architecture for DCT Computation Using Dynamic Partial Reconfiguration., , , and . ERSA, page 269-272. CSREA Press, (2008)Scalable Adaptive Spintronic Reconfigurable Logic Using Area-Matched MTJ Design., , , and . IEEE Trans. on Circuits and Systems, 63-II (7): 678-682 (2016)