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Using a Dynamically Reconfigurable System to Accelerate Octree Based 3D Graphics., , and . PDPTA, CSREA Press, (2000)SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems., , , , and . ERSA, page 174-180. CSREA Press, (2009)Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing., , , and . ERSA, page 119-125. CSREA Press, (2009)A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control., , , , , and . J. Solid-State Circuits, 48 (1): 8-19 (2013)CoreVA-MPSoC: A Many-Core Architecture with Tightly Coupled Shared and Local Data Memories., , , , , , , , and . IEEE Trans. Parallel Distrib. Syst., 29 (5): 1030-1043 (2018)A massively parallel architecture for self-organizing feature maps., , and . IEEE Trans. Neural Networks, 14 (5): 1110-1121 (2003)Exploiting dynamic partial reconfiguration for on-line on-demand testing of permanent faults in reconfigurable systems., , , , , , and . DFT, page 203-208. IEEE Computer Society, (2014)Mini-Robot's Performance Optimization via Online Reconfiguration and HW/SW Task Scheduling., , , , and . IPDPS Workshops, page 437-442. IEEE Computer Society, (2012)A holistic methodology for network processor design., , , , , , , , , and . LCN, page 583-. IEEE Computer Society, (2003)Design optimizations to improve placeability of partial reconfiguration modules., , , and . DATE, page 976-981. IEEE, (2009)