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Disambiguation of "Sachdev, Manoj"

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Optimizing Circuit Performance and ESD Protection for High-Speed Differential I/Os.

, , and . CICC, page 149-152. IEEE, (2007)

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Manoj Paneru University of Stuttgart

 

Other publications of authors with the same name

A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC., and . CICC, page 1-4. IEEE, (2014)A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs., , and . ITC, page 1108-1117. IEEE Computer Society, (2004)Voltage-Boosted Synchronizers., , , and . ACM Great Lakes Symposium on VLSI, page 307-312. ACM, (2015)IDDQ and Voltage Testable CMOS Flip-flop Configurations.. ITC, page 534-543. IEEE Computer Society, (1995)An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 µm CMOS., and . J. Solid-State Circuits, 44 (2): 620-630 (2009)Suppression of on-chip power supply noise generated by a 64-bit static logic ALU block., , , and . VLSI-SoC, page 201-206. IEEE, (2012)A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm., , and . VLSI-SoC, page 275-278. IEEE, (2012)A 0.8V Delta-Sigma modulator using DTMOS technique., and . ISCAS (4), page 3684-3687. IEEE, (2005)Correction to Ä Digitally Programmable Delay Element: Design and Analysis"., and . IEEE Trans. VLSI Syst., 12 (10): 1126-1126 (2004)DTMOS Technique for Low-Voltage Analog Circuits., and . IEEE Trans. VLSI Syst., 14 (10): 1151-1156 (2006)