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A 3D multi-layer CMOS-RRAM accelerator for neural network.

H. Huang, L. Ni, Y. Wang, H. Yu, Z. Wang, Y. Cai, and R. Huang. 3DIC, page 1-5. IEEE, (2016)

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Resistive switching in organic memory devices for flexible applications.R. Huang, Y. Cai, Y. Liu, W. Bai, Y. Kuang, and Y. Wang. ISCAS, page 838-841. IEEE, (2014)Novel vertical channel double gate structures for high density and low power flash memory applications.R. Huang, F. Zhou, Y. Cai, D. Wu, and X. Zhang. Science in China Series F: Information Sciences, 51 (6): 799-806 (2008)Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning.Q. Zheng, Z. Wang, J. Kang, Z. Yu, Y. Cai, and J. Xu. NVMTS, page 1-3. IEEE, (2018)Enhancement of HfO2 Based RRAM Performance Through Hexagonal Boron Nitride Interface Layer.Y. Chen, Z. Wang, Z. Zhang, L. Wang, Y. Fang, J. Lou, K. Liu, J. Xu, Y. Cai, and R. Huang. NVMTS, page 1-3. IEEE, (2018)An electronic synapse based on tantalum oxide material.X. Yang, Y. Cai, Z. Zhang, M. Yu, and R. Huang. NVMTS, page 1-4. IEEE, (2015)Rotational Pattern Recognition by Spiking Correlated Neural Network Based on Dual-Gated MoS 2 Neuristor.L. Bao, Z. Wang, Z. Yu, Y. Ling, Y. Cai, and R. Huang. Adv. Intell. Syst., 2 (11): 2000102 (2020)Editor's note.R. Huang, B. Zhao, R. Wang, and Y. Cai. SCIENCE CHINA Information Sciences, 54 (5): 913-914 (2011)Design and Implementation of a Peripheral Bus Based on a New Kind of Reconfigurable System.Y. Cai, Y. Zhao, and L. Lan. DASC, page 286-291. IEEE Computer Society, (2011)Margin Dependence on Array Size for Asymmetric Resistive Memory Cell.Z. Yu, Y. Fang, Z. Wang, Y. Cai, R. Huang, and J. Xu. NVMTS, page 1-3. IEEE, (2018)Influence of selector-introduced compliance current on HfOx RRAM switching operation.Y. Fang, Y. Cai, Z. Wang, Z. Yu, X. Yang, and R. Huang. NVMTS, page 1-3. IEEE, (2015)

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A 3D multi-layer CMOS-RRAM accelerator for neural network.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 3D multi-layer CMOS-RRAM accelerator for neural network.

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A 3D multi-layer CMOS-RRAM accelerator for neural network.