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Exploring a Low-Cost and Power-Efficient Hybridization Technique for 3D NoC-Bus Hybrid Architecture Using LastZ-Based Routing Algorithms.

A. Rahmani, P. Liljeberg, J. Plosila, and H. Tenhunen. J. Low Power Electronics, 8 (4): 403-414 (2012)

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Analysis of Monitoring Structures for Network-on-Chip: A Distributed Approach.V. Rantala, T. Lehtonen, P. Liljeberg, and J. Plosila. IJERTCS, 2 (1): 49-67 (2011)Design space exploration of thermal-aware many-core systems.K. Vaddina, A. Rahmani, M. Fattah, P. Liljeberg, and J. Plosila. Journal of Systems Architecture - Embedded Systems Design, 59 (10-D): 1197-1213 (2013)Thermal Analysis of Job Allocation and Scheduling Schemes for 3D Stacked NoC's.K. Vaddina, A. Rahmani, K. Latif, P. Liljeberg, and J. Plosila. DSD, page 643-648. IEEE Computer Society, (2011)Generation of Structural VHDL Code with Library Components from Formal Event-B Models.S. Ostroumov, L. Tsiopoulos, K. Sere, and J. Plosila. DSD, page 111-118. IEEE Computer Society, (2013)HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks.M. Ebrahimi, M. Daneshtalab, F. Farahnakian, J. Plosila, P. Liljeberg, M. Palesi, and H. Tenhunen. NOCS, page 19-26. IEEE Computer Society, (2012)Generic Monitoring and Management Infrastructure for 3D NoC-Bus Hybrid Architectures.A. Rahmani, K. Vaddina, K. Latif, P. Liljeberg, J. Plosila, and H. Tenhunen. NOCS, page 177-184. IEEE Computer Society, (2012)Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput.E. Nigussie, S. Tuuna, J. Plosila, J. Isoaho, and H. Tenhunen. IEEE Trans. VLSI Syst., 20 (12): 2265-2277 (2012)High-performance on-chip network platform for memory-on-processor architectures.M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen. ReCoSoC, page 1-6. IEEE, (2011)DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs.M. Tajammul, S. Jafri, P. Ellervee, A. Hemani, H. Tenhunen, and J. Plosila. VLSI Design, page 547-552. IEEE Computer Society, (2015)Customizable Compression Architecture for Efficient Configuration in CGRAs.S. Jafri, M. Tajammul, M. Daneshtalab, A. Hemani, K. Paul, P. Ellervee, J. Plosila, and H. Tenhunen. FCCM, page 31. IEEE Computer Society, (2014)

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Disambiguation of "Plosila, Juha"

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Exploring a Low-Cost and Power-Efficient Hybridization Technique for 3D NoC-Bus Hybrid Architecture Using LastZ-Based Routing Algorithms.

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Disambiguation of "Plosila, Juha"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Exploring a Low-Cost and Power-Efficient Hybridization Technique for 3D NoC-Bus Hybrid Architecture Using LastZ-Based Routing Algorithms.

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Exploring a Low-Cost and Power-Efficient Hybridization Technique for 3D NoC-Bus Hybrid Architecture Using LastZ-Based Routing Algorithms.