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A 140 GHz area-and-power-efficient VCO using frequency doubler in 65 nm CMOS.

Y. Otsuki, D. Yamazaki, N. Khanh, and T. Iizuka. IEICE Electronic Express, 16 (6): 20190051 (2019)

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A 140 GHz area-and-power-efficient VCO using frequency doubler in 65 nm CMOS.Y. Otsuki, D. Yamazaki, N. Khanh, and T. Iizuka. IEICE Electronic Express, 16 (6): 20190051 (2019)A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-µm Technology.H. Nakamoto, D. Yamazaki, T. Yamamoto, H. Kurata, S. Yamada, K. Mukaida, T. Ninomiya, T. Ohkawa, S. Masui, and K. Gotoh. J. Solid-State Circuits, 42 (1): 101-110 (2007)A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal.Y. Wang, D. You, X. Fu, T. Nakamura, A. Fadila, T. Someya, A. Kawaguchi, J. Qiu, J. Pang, K. Yanagisawa and 8 other author(s). IEEE J. Solid State Circuits, 57 (2): 356-370 (2022)

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A 140 GHz area-and-power-efficient VCO using frequency doubler in 65 nm CMOS.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 140 GHz area-and-power-efficient VCO using frequency doubler in 65 nm CMOS.

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A 140 GHz area-and-power-efficient VCO using frequency doubler in 65 nm CMOS.