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Disambiguation of "Li, Tun"

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Separation of communication and computation in SystemC/TLM modeling: A Feature-Oriented approach.

, , and . ISQED, page 481-485. IEEE, (2011)

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M.Sc. Yunxuan Li University of Stuttgart

Yu Li University of Stuttgart

Zheng Li University of Stuttgart

Jie Li University of Stuttgart

Li Zhong University of Stuttgart

 

Other publications of authors with the same name

Feature-Oriented Refactoring Proposal for Transaction Level Models in SoCLib., , , , and . FDL, page 22-27. ECSI, Electronic Chips & Systems design Initiative, (2010)2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions., , , and . ISQED, page 637-642. IEEE Computer Society, (2008)Applying Constraint Logic Programming to Predicate Abstraction of RTL Verilog Descriptions., , , and . MICAI, volume 3789 of Lecture Notes in Computer Science, page 175-184. Springer, (2005)Design and Implementation of a Parallel Verilog Simulator: PVSim., , and . VLSI Design, page 329-334. IEEE Computer Society, (2004)An Approximate Soft Error Reliability Sorting Approach Based on State Analysis of Sequential Circuits., , and . DFT, page 209-217. IEEE Computer Society, (2010)Explicit Model Checking Based on Integer Pointer and Fibonacci Hash., , , and . ICYCS, page 844-849. IEEE Computer Society, (2008)Equivalence Checking between SLM and TLM Using Coverage Directed Simulation., , and . CAD/Graphics, page 101-106. IEEE, (2013)Application specified soft error failure rate analysis using sequential equivalence checking techniques., , , and . ASP-DAC, page 608-613. IEEE, (2013)Efficient translation validation of high-level synthesis., , , and . ISQED, page 516-523. IEEE, (2013)A Novel Collaborative Verification Environment for SoC Co-Verification., , , and . CSCWD, page 145-150. IEEE, (2007)