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Row-buffer decoupling: A case for low-latency DRAM microarchitecture.

S. O, Y. Son, N. Kim, and J. Ahn. ISCA, page 337-348. IEEE Computer Society, (2014)

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Maximilian Overbeck

European debates during the Libya crisis of 2011: shared identity, divergent actionM. Overbeck. European Security, 23 (4): 583-600 (2014)

Hamza Oukili University of Stuttgart

Alexandra Christina Oßwald University of Stuttgart

Thomas Obst University of Stuttgart

Philipp Oestringer University of Stuttgart

Other publications of authors with the same name

Full-Stack Architecting to Achieve a Billion-Requests-Per-Second Throughput on a Single Key-Value Store Server Platform.S. Li, H. Lim, V. Lee, J. Ahn, A. Kalia, M. Kaminsky, D. Andersen, S. O, S. Lee, and P. Dubey. ACM Trans. Comput. Syst., 34 (2): 5:1-5:30 (2016)Achieving One Billion Key-Value Requests per Second on a Single Server.S. Li, H. Lim, V. Lee, J. Ahn, A. Kalia, M. Kaminsky, D. Andersen, S. O, S. Lee, and P. Dubey. IEEE Micro, 36 (3): 94-104 (2016)History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures.K. Chen, S. Li, J. Ahn, N. Muralimanohar, J. Zhao, C. Xu, S. O, Y. Xie, J. Brockman, and N. Jouppi. ICS, page 251-261. ACM, (2015)Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product.S. Lee, S. Kang, J. Lee, H. Kim, E. Lee, S. Seo, H. Yoon, S. Lee, K. Lim, H. Shin and 6 other author(s). ISCA, page 43-56. IEEE, (2021)CiDRA: A cache-inspired DRAM resilience architecture.Y. Son, S. Lee, S. O, S. Kwon, N. Kim, and J. Ahn. HPCA, page 502-513. IEEE Computer Society, (2015)25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications.Y. Kwon, S. Lee, J. Lee, S. Kwon, J. Ryu, J. Son, S. O, H. soo Yu, H. Lee, S. Kim and 20 other author(s). ISSCC, page 350-352. IEEE, (2021)3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions.S. Lee, K. Lee, M. Sung, M. Alian, C. Kim, W. Cho, R. Oh, S. O, J. Ahn, and N. Kim. PACT, page 22:1-22:12. ACM, (2018)Reducing memory access latency with asymmetric DRAM bank organizations.Y. Son, S. O, Y. Ro, J. Lee, and J. Ahn. ISCA, page 380-391. ACM, (2013)Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems.Y. Son, S. O, H. Yang, D. Jung, J. Ahn, J. Kim, J. Kim, and J. Lee. SC, page 1059-1070. IEEE, (2014)Row-buffer decoupling: A case for low-latency DRAM microarchitecture.S. O, Y. Son, N. Kim, and J. Ahn. ISCA, page 337-348. IEEE Computer Society, (2014)

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Disambiguation of "O, Seongil"

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Row-buffer decoupling: A case for low-latency DRAM microarchitecture.

Please choose a person to relate this publication to

Maximilian Overbeck

Hamza Oukili University of Stuttgart

Alexandra Christina Oßwald University of Stuttgart

Thomas Obst University of Stuttgart

Philipp Oestringer University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "O, Seongil"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Row-buffer decoupling: A case for low-latency DRAM microarchitecture.

Please choose a person to relate this publication to

Maximilian Overbeck

Hamza Oukili University of Stuttgart

Alexandra Christina Oßwald University of Stuttgart

Thomas Obst University of Stuttgart

Philipp Oestringer University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
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Row-buffer decoupling: A case for low-latency DRAM microarchitecture.