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Wear-aware Memory Management Scheme for Balancing Lifetime and Performance of Multiple NVM Slots.

C. Xiao, L. Cheng, L. Zhang, D. Liu, and W. Liu. MSST, page 148-160. IEEE, (2019)

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Di Liu University of Stuttgart

Narrow inhomogeneous distribution of spin-active emitters in silicon carbideR. Nagy, D. Dasari, C. Babin, D. Liu, V. Vorobyov, M. Niethammer, M. Widmann, T. Linkewitz, I. Gediz, R. Stöhr and 7 other author(s). Applied physics letters, 118 (14): 144003 (2021)Hybrids Made of Defective Nanodiamonds Interacting with DNA NucleobasesD. Liu, and M. Fyta. Nanotechnology, 30 (6): 065601 (2019)Spin-controlled generation of indistinguishable and distinguishable photons from silicon vacancy centres in silicon carbideN. Morioka, C. Babin, R. Nagy, I. Gediz, E. Hesselmeier, D. Liu, M. Joliffe, M. Niethammer, D. Dasari, V. Vorobyov and 10 other author(s). Nature Communications, (2020)

Jan Liu University of Stuttgart

M.Sc. Zhuoran Liu University of Stuttgart

Anji Liu University of Stuttgart

Dexing Liu University of Stuttgart

Other publications of authors with the same name

Efficient SAT-Based Mapping and Scheduling of Homogeneous Synchronous Dataflow Graphs for Throughput Optimization.W. Liu, M. Yuan, X. He, Z. Gu, and X. Liu. RTSS, page 492-504. IEEE Computer Society, (2008)Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.Y. Ye, J. Xu, X. Wu, W. Zhang, X. Wang, M. Nikdast, Z. Wang, and W. Liu. ISVLSI, page 254-259. IEEE Computer Society, (2011)Traffic-Aware Application Mapping for Network-on-Chip Based Multiprocessor System-on-Chip.L. Yang, W. Liu, W. Jiang, W. Zhang, M. Li, J. Yi, D. Liu, and E. Sha. HPCC/CSS/ICESS, page 571-576. IEEE, (2015)Enhancing lifetime of NVM-based main memory with bit shifting and flipping.X. Luo, D. Liu, K. Zhong, D. Zhang, Y. Lin, J. Dai, and W. Liu. RTCSA, page 1-7. IEEE Computer Society, (2014)Efficient Software Synthesis for Dynamic Single Appearance Scheduling of Synchronous Dataflow.W. Liu, Z. Gu, and J. Xu. Embedded Systems Letters, 1 (3): 69-72 (2009)An Efficient Technique of Application Mapping and Scheduling on Real-Time Multiprocessor Systems for Throughput Optimization.W. Liu, and C. Xiao. ACM Trans. Embedded Comput. Syst., 15 (4): 65:1-65:25 (2016)Analyzing Data Cache Related Preemption Delay With Multiple Preemptions.W. Zhang, N. Guan, L. Ju, and W. Liu. IEEE Trans. on CAD of Integrated Circuits and Systems, 37 (11): 2255-2265 (2018)Timing-Anomaly Free Dynamic Scheduling of Conditional DAG Tasks on Multi-Core Systems.P. Chen, W. Liu, X. Jiang, Q. He, and N. Guan. ACM Trans. Embedded Comput. Syst., 18 (5s): 91:1-91:19 (2019)Design of a Hierarchical Clos-Benes Optical Network-on-Chip Architecture.R. Yao, Y. Ye, and W. Liu. ISVLSI, page 523-528. IEEE, (2019)TaiJiNet: Towards Partial Binarized Convolutional Neural Network for Embedded Systems.Y. Ling, K. Zhong, Y. Wu, D. Liu, J. Ren, R. Liu, M. Duan, W. Liu, and L. Liang. ISVLSI, page 136-141. IEEE Computer Society, (2018)

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Disambiguation of "Liu, Weichen"

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Wear-aware Memory Management Scheme for Balancing Lifetime and Performance of Multiple NVM Slots.

Please choose a person to relate this publication to

Di Liu University of Stuttgart

Jan Liu University of Stuttgart

M.Sc. Zhuoran Liu University of Stuttgart

Anji Liu University of Stuttgart

Dexing Liu University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Liu, Weichen"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Wear-aware Memory Management Scheme for Balancing Lifetime and Performance of Multiple NVM Slots.

Please choose a person to relate this publication to

Di Liu University of Stuttgart

Jan Liu University of Stuttgart

M.Sc. Zhuoran Liu University of Stuttgart

Anji Liu University of Stuttgart

Dexing Liu University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
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Wear-aware Memory Management Scheme for Balancing Lifetime and Performance of Multiple NVM Slots.