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Disambiguation of "Valls, Javier"

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Performance evaluation of fine time synchronizers for WLANs.

, , , and . EUSIPCO, page 1-4. IEEE, (2005)

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Javier Aguilar Romero University of Stuttgart

Dr. Ferran Giones Valls University of Stuttgart

Andres Javier Zeller University of Stuttgart

Javier Andres Carrillo Delcorto University of Stuttgart

 

Other publications of authors with the same name

A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems., , , , and . PIMRC, page 531-535. IEEE, (2004)Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes., , , and . Signal Processing Systems, 68 (2): 139-149 (2012)Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes., , , and . IEEE Trans. VLSI Syst., 22 (11): 2256-2267 (2014)Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain., , and . Int. J. Reconfig. Comp., (2014)Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems., , , and . CSSP, 38 (4): 1793-1810 (2019)FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices., , , , , and . IEEE Trans. Education, 50 (3): 229-235 (2007)50 Years of CORDIC: Algorithms, Architectures, and Applications., , , , and . IEEE Trans. on Circuits and Systems, 56-I (9): 1893-1907 (2009)Power analysis and estimation tool integrated with XPOWER., , , and . FPGA, page 259. ACM, (2004)Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes., , , and . Signal Processing Systems, 66 (2): 99-104 (2012)Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms., and . FPL, page 472-475. IEEE, (2007)