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Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems., , , and . RTSS, page 230-241. IEEE Computer Society, (2018)A hardware architecture to deploy complex multiprocessor scheduling algorithms., , , and . RTCSA, page 1-10. IEEE Computer Society, (2014)Deterministic Memory Abstraction and Supporting Multicore System Architecture., , , and . ECRTS, volume 106 of LIPIcs, page 1:1-1:25. Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, (2018)A real-time scratchpad-centric OS with predictable inter/intra-core communication for multi-core embedded systems., , , , and . Real-Time Systems, 55 (4): 850-888 (2019)Real-time cache management framework for multi-core architectures., , , , , and . IEEE Real-Time and Embedded Technology and Applications Symposium, page 45-54. IEEE Computer Society, (2013)A Memory Access Detection Methodology for Accurate Workload Characterization., , , and . RTCSA, page 141-148. IEEE Computer Society, (2015)Deterministic Memory Abstraction and Supporting Cache Architecture for Real-Time Systems., , , and . CoRR, (2017)Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms., , , , , and . ECRTS, volume 133 of LIPIcs, page 27:1-27:25. Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, (2019)Restart-Based Fault-Tolerance: System Design and Schedulability Analysis., , , and . CoRR, (2017)From Molecular Activities and Processes to Biological Function., , , , , and . Briefings in Bioinformatics, 2 (1): 81-107 (2001)