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Disambiguation of "El-Maleh, Aiman H."

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Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation.

, , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (11): 2556-2564 (2006)

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H. Binz

H. Bungartz

H. Binz

Ahmed Elkelesh University of Stuttgart

Florian Elben University of Stuttgart

 

Other publications of authors with the same name

Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (11): 2556-2564 (2006)A probabilistic pairwise swap search state assignment algorithm for sequential circuit optimization.. Integration, (2017)Efficient test compression technique based on block merging.. IET Computers & Digital Techniques, 2 (5): 327-335 (2008)Test data compression for system-on-a-chip using extended frequency-directed run-length code.. IET Computers & Digital Techniques, 2 (3): 155-163 (2008)A static test compaction technique for combinational circuits based on independent fault clustering., and . ICECS, page 1316-1319. IEEE, (2003)An Efficient Test Relaxation Technique for Synchronous Sequential Circuits., and . VTS, page 179-185. IEEE Computer Society, (2003)On efficient extraction of partially specified test sets for synchronous sequential circuits., and . ISCAS (5), page 545-548. IEEE, (2003)A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy., , , and . IEEE Trans. VLSI Syst., 25 (1): 224-237 (2017)Defect-tolerant n2-transistor structure for reliable nanoelectronic designs., , , and . IET Computers & Digital Techniques, 3 (6): 570-580 (2009)A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits., and . Microelectronics Reliability, 54 (1): 316-326 (2014)