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A high-performance reconfigurable 2-D transform architecture for H.264.

, , , , and . ICECS, page 606-609. IEEE, (2008)

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FPART: A Multi-way FPGA Partitioning Procedure Based on the Improved FM Algorithm., , and . ASP-DAC, page 513-518. IEEE, (1998)A Reconfigurable Multi-Transform VLSI Architecture Supporting Video Codec Design., , , , , and . IEEE Trans. on Circuits and Systems, 58-II (7): 432-436 (2011)A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only)., and . FPGA, page 263. ACM, (2005)High-speed and memory-efficient architecture for 2-D 1-Level discrete wavelet transform., , , , and . ICECS, page 486-489. IEEE, (2008)A novel dynamic reconfigurable VLSI architecture for H.264 transforms., , , , and . APCCAS, page 1810-1813. IEEE, (2008)Engineering a scalable Boolean matching based on EDA SaaS 2.0., , , , and . ICCAD, page 750-755. IEEE, (2010)A high-performance reconfigurable VLSI architecture for vbsme in H.264., , , , and . IEEE Trans. Consumer Electronics, 54 (3): 1338-1345 (2008)Frequency domain wavelet method with GMRES for large-scale linear circuit simulation., , , , , and . ISCAS (5), page 321-324. IEEE, (2004)General switch box modeling and optimization for FPGA routing architectures., , , , and . FPT, page 320-323. IEEE, (2010)Yet Another Many-Objective Clustering (YAMO-Pack) for FPGA CAD., , and . FPL, page 1-4. IEEE, (2013)