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A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS.

S. Gopal, P. Agarwal, J. Baylon, L. Renaud, S. Ali, P. Pande, and D. Heo. IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 506-518 (2018)

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Michael Pandey University of Stuttgart

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Timing analysis of network on chip architectures for MP-SoC platforms.C. Grecu, P. Pande, A. Ivanov, and R. Saleh. Microelectronics Journal, 36 (9): 833-845 (2005)Wireless NoC Platforms With Dynamic Task Allocation for Maximum Likelihood Phylogeny Reconstruction.T. Majumder, P. Pande, and A. Kalyanaraman. IEEE Design & Test, 31 (3): 54-64 (2014)Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding.P. Pande, A. Ganguly, B. Feero, B. Belzer, and C. Grecu. DFT, page 466-476. IEEE Computer Society, (2006)An energy-efficient millimeter-wave wireless NoC with congestion-aware routing and DVFS.R. Kim, J. Murray, P. Wettin, P. Pande, and B. Shirazi. NOCS, page 192-193. IEEE, (2014)Sustainable and Reliable On-Chip Wireless Communication Infrastructure for Massive Multi-core Systems.A. Ganguly, P. Pande, B. Belzer, and A. Nojeh. Evolutionary Based Solutions for Green Computing, volume 432 of Studies in Computational Intelligence, Springer, (2013)On-Chip Network-Enabled Multicore Platforms Targeting Maximum Likelihood Phylogeny Reconstruction.T. Majumder, M. Borgens, P. Pande, and A. Kalyanaraman. IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (7): 1061-1073 (2012)Enhancing performance of wireless NoCs with distributed MAC protocols.K. Duraisamy, R. Kim, and P. Pande. ISQED, page 406-411. IEEE, (2015)A Scalable Communication-Centric SoC Interconnect Architecture.C. Grecu, P. Pande, A. Ivanov, and R. Saleh. ISQED, page 343-348. IEEE Computer Society, (2004)DVFS-enabled sustainable wireless NoC architecture.J. Murray, P. Pande, and B. Shirazi. SoCC, page 301-306. IEEE, (2012)Editorial.P. Pande. IEEE Trans. Multi-Scale Computing Systems, 2 (1): 1 (2016)

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Disambiguation of "Pande, Partha Pratim"

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A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS.

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Michael Pandey University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Pande, Partha Pratim"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS.

Please choose a person to relate this publication to

Michael Pandey University of Stuttgart

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Disambiguation

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URL
DOI
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A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS.