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Spin-Based Reconfigurable Logic for Power- and Area-Efficient Applications., , , , and . IEEE Design & Test, 36 (3): 22-30 (2019)Investigating modern layout representations for improved 3d design automation., , and . ACM Great Lakes Symposium on VLSI, page 337-342. ACM, (2011)Attacking Split Manufacturing from a Deep Learning Perspective., , , , , , , and . DAC, page 135. ACM, (2019)Planning Massive Interconnects in 3-D Chips., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (11): 1808-1821 (2015)SMART: Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory., , , , and . CoRR, (2019)Multi-Objective 3D Floorplanning with Integrated Voltage Assignment., , and . ACM Trans. Design Autom. Electr. Syst., 23 (2): 22:1-22:27 (2018)Protect Your Chip Design Intellectual Property: An Overview., , and . COINS, page 211-216. ACM, (2019)Multiobjective optimization of deadspace, a critical resource for 3D-IC integration., , , and . ICCAD, page 705-712. ACM, (2012)GNN4REL : Graph Neural Networks for Predicting Circuit Reliability Degradation, , , , and . 41, 11, page 3826-3837. IEEE, (2022)Power Side-Channel Attacks in Negative Capacitance Transistor, , , , , , , and . IEEE micro, 40 (6): 74-84 (2020)