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Disambiguation of "Mitsuhashi, Takashi"

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A layout checking system for large scale integrated circuits.

, , , , , and . DAC, page 322-330. ACM, (1977)

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Other publications of authors with the same name

A Resistance Calculation Algorithm and Its Application to Circuit Extraction., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 6 (3): 337-345 (1987)A Clock-Gating Method for Low-Power LSI Design., , , , , , and . ASP-DAC, page 307-312. IEEE, (1998)Switching activity analysis using Boolean approximation method., , , and . ICCAD, page 20-25. IEEE Computer Society / ACM, (1995)FOLM-Planner: A New Floorplanner with a Frame Overlapping Floorplan Model Suitable for SOG (Sea-of-Gates) Type Gate Arrays., , and . ICCAD, page 140-143. IEEE Computer Society, (1990)Switching activity analysis for sequential circuits using Boolean approximation method., , , and . ISLPED, page 79-84. IEEE, (1996)Usage Distribution Coverage: What Percentage of Expected Use Has Been Executed in Software Testing?, , , , and . Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, volume 209 of Studies in Computational Intelligence, Springer, (2009)An integrated mask artwork analysis system., , , and . DAC, page 277-284. ACM/IEEE, (1980)Power and Ground Network Topology Optimization for Cell Based VLSIs., and . DAC, page 524-529. (1992)A layout checking system for large scale integrated circuits., , , , , and . DAC, page 322-330. ACM, (1977)Fanout-tree restructuring algorithm for post-placement timing optimization., , , and . ASP-DAC, ACM, (1995)